1. Field of the Invention
This invention relates to a static random access memory (SRAM) cell and, in particular to an SRAM cell having open-base, bipolar load elements.
2. Description of the Prior Art
Static random access memory (SRAM) chips are well known in the art. An SRAM chip is conventionally structured in rows and columns of individual SRAM cells. A prior art six transistor SRAM cell is shown schematically in FIG. 1. SRAM cell 1 includes two p-type transistors 7 and 8, and four n-type transistors 5, 6, 9 and 10. SRAM cell 1 has two states: logic state "0" and logic state "1" . By convention, if logic state "0" is designated by node A having a low voltage and node B having a high voltage, then logic state "1" has the opposite stored voltages, i.e. node A having a high voltage and node B having a low voltage.
In logic state "0" the low voltage on node A turns off transistor 9 and turns on transistor 7, whereas the high voltage on node B turns on transistor 10 and turns off transistor 8. Because transistor 10 is on and transistor 8 is off, current flows through transistor 10 to voltage supply Vss (ground), thereby maintaining a low voltage on node A. Because transistor 7 is turned on and transistor 9 is turned off, current flows from voltage supply Vcc through transistor 7, thereby maintaining a high voltage on node B.
To change the state of SRAM cell 1 from a logic "0" to a logic "1" bit line 3 and bit line 2 are provided with a high and a low voltage, respectively. Then, access transistors 5 and 6 are turned on by a high voltage on word line 4, thereby providing the high voltage on bit line 3 to node A and the low voltage on bit line complement 2 to node B. Accordingly, transistor 9 is turned on and transistor 7 is turned off by the high voltage on node A and transistor 10 is turned off and transistor 8 is turned on by the low voltage on node B, thereby switching the state of the circuit from logic "0" to logic "1". Following the switching of the state of cell 1, access transistors 5 and 6 are turned off (by applying a low voltage on word line 4). Cell 1 maintains its new logic state in a manner analogous to that described above.
FIG. 2 illustrates one example of a cell layout of the six transistor SRAM cell 1 shown in FIG. 1. For cell stability the driver transistors 9, 10 should have a W/L ratio at least a factor of 2 greater than the W/L ratio of access transistors 5, 6. See the article by E. Seevinck et al., entitled Static Noise Margin Analysis of MOS SRAM Cells, IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, at 748-54 (October 1987). The pullup transistors 7, 8 usually have the smallest W/L possible as allowed by the technology design rules.
SRAM cell 1 of FIGS. 1 and 2 occupies a large area on the chip surface due to the formation of the required six transistors, i.e. transistors 5-10. Moreover, node B, which is coupled to both transistors 7 and 10 as shown in FIGS. 1 and 2, requires a metal interconnect line between these two transistors. Using single layer metal technology, the six-transistor memory cell, i.e. SRAM cell 1, requires at least five widths of metal interconnect, which effectively determines the size of cell 1. These five widths include the metal for bit lines 2 and 3, the metal for nodes A and B, and the metal for voltage supply VSS. Using double layer metal technology (as in FIG. 2), the metal for bit lines 2 and 3 is positioned above the metal for nodes A and B. Thus, for double layer metal, SRAM cell 1 requires only three widths of metal interconnect.
In another prior art SRAM cell 12, shown in FIG. 3, p-type transistors 7 and 8 of FIGS. 1 and 2 are replaced by load resistors 13 and 14, wherein each resistor has a high resistance of, for example, 1.times.10.sup.8 to 1.times.10.sup.10 ohms. The replacement of transistors 7 and 8 with resistors 13 and 14 decreases the size of memory cell 12. However, the high resistance values of load resistors 13 and 14 increases the power consumption in cell 12. Although it is well known in the art to produce high resistance resistors on a small surface area by using ion-implanted polysilicon to provide the desired resistance level, there are a number of serious problems to be overcome.
For example, controlling the resistance of polysilicon during fabrication is extremely difficult. Although load resistors 13 and 14 may be fabricated from the same layer of polysilicon used to form the polysilicon gates of transistors 5, 6, 9, and 10, typically two polysilicon layers are necessary. Specifically, one polysilicon layer is used for load resistors 13 and 14 and another polysilicon layer is used for the gates of transistors 5 and 6, and supply voltage Vcc. For example, FIG. 4 illustrates a cross section of a portion of SRAM cell 12 having a first polysilicon layer 20 for supply voltage Vcc and gate G, and a second polysilicon layer 21 for a resistor R.
However, even if SRAM cell 12 is fabricated with two polysilicon layers, SRAM cell 12 still has several disadvantages. First, referring back to FIG. 3, load resistors 13 and 14 are fabricated by a complex process which produces devices having substantial variations in resistance. These variations result in low yield for such processes. Second, load resistors 13 and 14 must provide a current which is higher than the leakage current, i.e. typically in the range of 2-10.times.10.sup.-14 amps, from nodes A and B while not exceeding a level of current that creates a stand-by current problem. Providing a suitable load resistor which has a high enough resistance to provide a current in this range is difficult because the load resistor must have a very high resistance, yet must occupy only a small area of the chip surface. As the density of SRAM cells in an array increases, the operating window for the resistance variation of load resistors becomes smaller. This phenomena is described in detail in an article by Stephen Flannagan, entitled Future Technology Trends For Static Rams, 1988 IEEE International Electron Devices Meeting Technical Digest, 40-43.
Integrating an electrically erasable programmable read only memory (EPROM) or flash EPROM cell into the same die with an SRAM cell further complicates the process of making an SRAM cell with polysilicon resistors. For example, a number of process steps performed during fabrication of a conventional EPROM or flash EPROM cell, in particular for a polysilicon floating gate and control gate, are incompatible with the process steps performed during fabrication of the high resistance polysilicon load resistors 13 and 14. To form an EPROM or flash EPROM cell requires two polysilicon layers. Specifically, to provide an SRAM cell with polysilicon resistors and an EPROM or flash EPROM cell on the same wafer requires three polysilicon layers: a first layer for the floating gate, a second layer for the control gate and word line, and a third layer for the polysilicon load resistor. Moreover, after fabrication of the high resistance polysilicon load resistors 13 and 14, cell 12 cannot tolerate any further high temperature processing steps. Thus, fabrication of an EPROM or flash EPROM cell on the same wafer as a polysilicon load resistor necessitates additional processing steps and significantly reduces the type of processing steps which can be performed.
Thus, a need arises for an SRAM cell load element which compensates for a leakage current and, at the same time, is easily integrated with an EPROM or flash EPROM cell on the same wafer, thereby reducing board size and providing faster performance at reduced cost.